1. Field of the Invention
The present invention relates to a process for fabricating a semiconductor device, and more particularly, to a method for forming a plug of a semiconductor device that improves characteristic of the semiconductor device and its structure.
2. Background of the Related Art
Generally, a poly plug is formed using polysilicon in a DRAM and a logic device. Recently, with the reduction of the design rule, a chemical mechanical polishing (CMP) process is used to form a poly plug, instead of an etch back process.
Two methods for forming a poly plug using CMP process have been suggested.
One method is to form a poly plug using the CMP process after contact etching.
The other is a method for forming a line poly plug by depositing polysilicon and then etching it by the CMP process. In this method, the CMP process may be performed to form a line poly plug directly after a later process is performed on a wordline pattern and polysilicon is deposited thereon. In this case, a height difference of a plug may occur due to a density difference of a lower structure (gate pattern). To minimize such height difference, after forming polysilicon, polysilicon in a portion where lower pattern density is high may partially be removed by an etching process and then a plug is formed by the CMP process.
The first related art method for forming a plug of a semiconductor device will be described with reference to the accompanying drawings. In this method, a poly plug is formed within a contact hole using the CMP process.
FIGS. 1a to 1f are sectional views showing the first related art method for forming a plug of a semiconductor device.
As shown in FIG. 1a, a first polysilicon film 11 and a cap insulating film 12 for a wordline are sequentially formed on a semiconductor substrate 10 in which a cell region and a peripheral region are defined.
The first polysilicon film 11 and the cap insulating film 12 are selectively removed to densely form the wordline in the cell region and sparsely form the wordline in the peripheral region.
An insulating film 13 is formed on an entire surface of the semiconductor substrate 10 including the cap insulating film 12. A first photoresist (not shown) is then deposited on the insulating film 13 and patterned to expose the cell region only.
Insulating film spacers 13a are formed at both sides of the cap insulating film 12 and the first polysilicon film 11 by performing etch-back process in the exposed cell region, and the first photoresist is removed.
As shown in FIGS. 1b and 1c, an inter layer dielectric (ILD) film 14 is formed on the entire surface of the semiconductor substrate 10 and then planarized by the CMP process.
As shown in FIG. 1d, a second photoresist (not shown) is deposited on the entire surface and then patterned by exposure and developing processes to define a contact region.
The ILD film 14 is selectively removed using the patterned photoresist as a mask to partially expose the surface of the semiconductor substrate 10. Thus, a contact hole 15 is formed and the second photoresist is removed.
As shown in FIGS. 1e and 1f, a second polysilicon film 16 is formed on the entire surface including the contact hole 15, and the CMP process is performed using the ILD film 14 as an end point to form a poly plug 16a within the contact hole 15. The poly plug 16a electrically connects an upper structure with the semiconductor substrate.
The second method for forming a poly plug by an etching process after forming a polysilicon line of a damascene structure will now be described.
FIGS. 2a to 2c are sectional views showing the second related art method for forming a plug of a semiconductor device.
As shown in FIG. 2a, a first polysilicon film 21 and a cap insulating film 22 for a wordline are sequentially formed on a semiconductor substrate 20 in which a cell region and a peripheral region are defined.
The first polysilicon film 21 and the cap insulating film 22 are selectively removed to densely form the wordline in the cell region and sparsely form the wordline in the peripheral region.
An insulating film 23 is formed on an entire surface of the semiconductor substrate 20. A photoresist (not shown) is then deposited on the insulating film 23 and patterned to expose the cell region only.
Insulating film spacers 23a are formed at both sides of the cap insulating film 22 and the first polysilicon film 21 by performing etch-back process in the exposed cell region, and the photoresist is removed.
As shown in FIGS. 2b and 2c, a second polysilicon film 24 is formed on the entire surface of the semiconductor substrate 20, and the CMP process is performed using the cap insulating film 22 as an end point to form a poly plug 24a in a space between the insulating film spacers 23a of the cell region and around the wordline of the peripheral region.
At this time, it is difficult for the end point to be detected during the CMP process due to density difference of the wordline pattern in the cell region and the peripheral region. For this reason, the first polysilicon film 21 and the poly plug 24a in the peripheral region are damaged, thereby generating a step difference between the poly plug 24a of the cell region and the poly plug 24a of the peripheral region.
To solve the above problem according to the second related art method for forming a plug of a semiconductor device, the third related art method for forming a plug of a semiconductor device will be described with reference to FIGS. 3a to 3d. 
FIGS. 3a to 3d are sectional views showing the third related art method for forming a plug of a semiconductor device.
As shown in FIG. 3a, a first polysilicon film 31 and a cap insulating film 32 for a wordline are sequentially formed on a semiconductor substrate 30 in which a cell region and a peripheral region are defined.
The first polysilicon film 31 and the cap insulating film 32 are selectively removed to densely form the wordline in the cell region and sparsely form the wordline in the peripheral region.
An insulating film 33 is formed on an entire surface of the semiconductor substrate 30 in which the wordline is formed. A photoresist (not shown) is then deposited on the insulating film 33 and patterned to expose the cell region only.
Insulating film spacers 33a are formed at both sides of the cap insulating film 32 and the first polysilicon film 31 by performing etch-back process in the exposed cell region, and the photoresist is removed.
As shown in FIGS. 3b and 3c, a second polysilicon film 34 is formed on the entire surface of the semiconductor substrate 30. A photoresist (not shown) is then deposited on the entire surface and patterned by exposure and developing processes.
The second polysilicon film 34 on the wordline densely formed in the cell region is removed using the patterned photoresist as a mask, and the photoresist is removed.
As shown in FIG. 3d, the CMP process is performed using the cap insulating film 32 as an end point to form a poly plug 34a in a space around both the insulating film spacers 33a of the cell region and the wordline of the peripheral region.
However, the aforementioned related art methods for forming a plug of a semiconductor device have several problems.
First, the CMP process of polysilicon causes a height difference of the poly plug due to pattern density of the lower structure (wordline pattern).
The third related art method to solve the first problem has a problem in ensuring a process margin according to the formation of polysilicon and the etch-back process. The third related art method also has a problem in detecting the end point essentially required in the CMP process.
Furthermore, in the third related art method, a photolithography process is additionally performed to minimize the height difference of the poly plug. Thus, the process becomes more complicated and costly.
Accordingly, the present invention is directed to a method for forming a plug of a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method for forming a plug of a semiconductor device in which a height difference due to a density difference of a lower structure is reduced when forming a plug by CMP, so as to improve characteristic of the device and its structure.
Additional advantages, objects, and features of the invention will be set forth in part in the description which follows and in part will become apparent to those having ordinary skill in the art upon examination of the following or may be learned from practice of the invention. The objects and advantages of the invention may be realized and attained as particularly pointed out in the appended claims.
To achieve these and other advantages and in accordance with the purpose of the present invention, as embodied and broadly described, a method for forming a plug of a semiconductor device according to the present invention includes the steps of: forming a plurality of wordlines over a semiconductor substrate in which a cell region and a peripheral region are defined; forming a cap insulating film on the respective wordlines; forming a first insulating film over the semiconductor substrate including the cap insulating film; forming first insulating film spacers at both sides of the wordlines formed in the cell region; sequentially forming a conductive film and a second insulating film over the semiconductor substrate; selectively removing the second insulating film to expose a top surface of the conductive film; and selectively removing the conductive film and the second insulating film to expose a surface of the cap insulating film in the cell region.
These and other advantages are also achieved by providing a method of forming a plug of a semiconductor device, comprising sequentially forming a conductive film and an insulation film over a semiconductor substrate having a high density region and a low density region, the high density region have a greater number of structures formed thereover than the low density region; performing a first CMP (chemical mechanical polishing) process, in which slurry for removing insulating film is used, to selectively remove the insulating film and expose a top surface of the conductive film; and performing a second CMP process, in which slurry for removing conductive film is used, to selectively remove the conductive film and the insulating film and expose structures in the high density region.
It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory and are intended to provide further explanation of the invention as claimed.